-- Rejestr 8-bitowy
-- Wejscie danych: DATAIN[7..0]
-- Wyjscie danych: DATAOUT[7..0]
-- Wejscia sterujace:
-- IE# (input enable)
-- OE# (output enable)

library IEEE;
use IEEE.Std_Logic_1164.all;

entity REG8 is
  generic (delay : time := 5 ns);
  port (IE, OE  : in std_logic;
        DATAIN  : in std_logic_vector(7 downto 0);
        DATAOUT : out std_logic_vector(7 downto 0));
end entity REG8;

architecture REG8_arch of REG8 is
begin
  process(IE, OE, DATAIN)
    variable buf : std_logic_vector(7 downto 0);
  begin
    if (IE = '0') then
      buf := DATAIN;
    end if;
    if (OE = '0') then
      DATAOUT <= buf after delay;
      else DATAOUT <= "ZZZZZZZZ" after delay;
    end if;
  end process;
end architecture REG8_arch;


